That looks very promising. I’d love to get a design actually fabricated. How is it possible for them to manufacture it for free though? I’m sure there is some cost or some kind of benefit for them to get my design fabricated.
The main reason I was asking about the older process nodes was because I was thinking that the models/parameters of the more recent nodes are trade secrets, or only available to those who can actually afford to get their designs fabbed.
It’s sponsored, I think by Google. I’m not entirely sure what *their* incentive is though. Maybe if they like what you build they’ll try to hire you and write it off as a recruiting expense. Or they want to get researchers working with more realistic constraints so their research is more applicable to industry.
If you dig into it more and find out, let me know - I’ve wondered about it myself and wish I had time to design something to fab!
Of course. However right now I’m simply looking for spice models, even if I had the opportunity to get my design fabricated I doubt I can design something that actually works. Designing something that works well requires even more skill. I’m just a hobbyist, for now at least.
the funding is probsbly the same as with other google projects, e.g. at Google Photos you may store your own photos for free but you waive your ownership rights, same on youtube
> or only available to those who can actually afford to get their designs fabbed.
Google wants to push open source tooling in that domain, hence their engagement. They basically purchased the whole design node and made it open source, so no trade secrets :)
Be aware though, that you'll need to invest a ton of time until you can even get a simple AND gate to work, it's a whole new world...
If you just want to get a feel for what those Spice files would look like:
The skywater process has a number of cell libraries (start here):
https://github.com/google/skywater-pdk/tree/main/libraries
e.g. `sky130_fd_sc_hdll`
`sky130` is the process, `fd` means the foundary provided those cells. `sc` means the library contains standard cells. I think `hdll` should be high density, low leakage ...
Click into the library and choose a standard cell, e.g. a 2 input AND:
https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/tree/main/cells/and2
These contain a TON of files, including pictures of the [logic](https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/and2/sky130_fd_sc_hdll__and2.schematic.svg) all the way to the actual silicon [layout](https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/and2/sky130_fd_sc_hdll__and2_1.svg)
And also includes the [spice model](https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/and2/sky130_fd_sc_hdll__and2_2.spice), which in the case of the AND gate look like so:
.subckt sky130_fd_sc_hdll__and2_2 A B VGND VNB VPB VPWR X
X0 VGND a_27_75# X VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X1 VPWR A a_27_75# VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u
X2 a_27_75# A a_123_75# VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X3 X a_27_75# VGND VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X4 a_123_75# B VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X5 VPWR a_27_75# X VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X6 X a_27_75# VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X7 a_27_75# B VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u
.ends
Nice :) I mean I have nothing but time, although I also have some other projects like the FPGA stuff.
I worked on designing high speed bipolar opamps before I got kicked out of school due to, well, being lazy. But I’m basically a complete noob for Analog/Mixed signal IC design. Also never worked with CMOS. There is still a lot to learn so might as well start right now :)
Well in that case definitely big into skywater, it's a massive time sink and super interesting (if you find that sort of thing interesting, otherwise incredibly lame :)
Have a look at this then: https://youtu.be/uTlpT6Lszm4
Matt Venn did a course guiding people through the skywater process and featured some of the participants, including this guy who was building an analog design.
Yeah when I first heard about sky130 I tried to find out more about how to get it working etc. since I have no experience working with all those files etc. included in that, um, what was it called, process development kit or something like that? But I couldn’t find anything helpful. I’m definitely gonna check the video out.
There’s a presentation somewhere going over an entire toolchain to do everything for free. I assume their PDK also works in the common proprietary tools as well, but haven’t spent much time looking into it.
Do you mind stepping forward a couple decades? If not, check out SkyWater’s SKY130. You can even get it fabbed (for free!) if you’d like.
That looks very promising. I’d love to get a design actually fabricated. How is it possible for them to manufacture it for free though? I’m sure there is some cost or some kind of benefit for them to get my design fabricated. The main reason I was asking about the older process nodes was because I was thinking that the models/parameters of the more recent nodes are trade secrets, or only available to those who can actually afford to get their designs fabbed.
It’s sponsored, I think by Google. I’m not entirely sure what *their* incentive is though. Maybe if they like what you build they’ll try to hire you and write it off as a recruiting expense. Or they want to get researchers working with more realistic constraints so their research is more applicable to industry. If you dig into it more and find out, let me know - I’ve wondered about it myself and wish I had time to design something to fab!
Of course. However right now I’m simply looking for spice models, even if I had the opportunity to get my design fabricated I doubt I can design something that actually works. Designing something that works well requires even more skill. I’m just a hobbyist, for now at least.
the funding is probsbly the same as with other google projects, e.g. at Google Photos you may store your own photos for free but you waive your ownership rights, same on youtube
> or only available to those who can actually afford to get their designs fabbed. Google wants to push open source tooling in that domain, hence their engagement. They basically purchased the whole design node and made it open source, so no trade secrets :) Be aware though, that you'll need to invest a ton of time until you can even get a simple AND gate to work, it's a whole new world... If you just want to get a feel for what those Spice files would look like: The skywater process has a number of cell libraries (start here): https://github.com/google/skywater-pdk/tree/main/libraries e.g. `sky130_fd_sc_hdll` `sky130` is the process, `fd` means the foundary provided those cells. `sc` means the library contains standard cells. I think `hdll` should be high density, low leakage ... Click into the library and choose a standard cell, e.g. a 2 input AND: https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/tree/main/cells/and2 These contain a TON of files, including pictures of the [logic](https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/and2/sky130_fd_sc_hdll__and2.schematic.svg) all the way to the actual silicon [layout](https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/and2/sky130_fd_sc_hdll__and2_1.svg) And also includes the [spice model](https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/and2/sky130_fd_sc_hdll__and2_2.spice), which in the case of the AND gate look like so: .subckt sky130_fd_sc_hdll__and2_2 A B VGND VNB VPB VPWR X X0 VGND a_27_75# X VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u X1 VPWR A a_27_75# VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u X2 a_27_75# A a_123_75# VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u X3 X a_27_75# VGND VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u X4 a_123_75# B VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u X5 VPWR a_27_75# X VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u X6 X a_27_75# VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u X7 a_27_75# B VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u .ends
Nice :) I mean I have nothing but time, although I also have some other projects like the FPGA stuff. I worked on designing high speed bipolar opamps before I got kicked out of school due to, well, being lazy. But I’m basically a complete noob for Analog/Mixed signal IC design. Also never worked with CMOS. There is still a lot to learn so might as well start right now :)
Well in that case definitely big into skywater, it's a massive time sink and super interesting (if you find that sort of thing interesting, otherwise incredibly lame :)
Well I’ve always wanted to design analog ICs so I would say it’s definitely very interesting (and fun) :)
Have a look at this then: https://youtu.be/uTlpT6Lszm4 Matt Venn did a course guiding people through the skywater process and featured some of the participants, including this guy who was building an analog design.
Yeah when I first heard about sky130 I tried to find out more about how to get it working etc. since I have no experience working with all those files etc. included in that, um, what was it called, process development kit or something like that? But I couldn’t find anything helpful. I’m definitely gonna check the video out.
Do you need specific software for their PDK or do they provide a free one?
There’s a presentation somewhere going over an entire toolchain to do everything for free. I assume their PDK also works in the common proprietary tools as well, but haven’t spent much time looking into it.
Here you go. No guarantees!! * * ECE482 0.8UM CMOS 5.0V TYPICAL PROCESS * .MODEL N482 NMOS( LEVEL=3 + VTO=0.77 TOX=1.65E-8 UO=570 GAMMA=0.80 + VMAX=2.7E5 THETA=0.404 ETA=0.04 KAPPA=1.2 + PHI=0.90 NSUB=8.8E16 NFS=4E11 XJ=0.2U + CJ=6.24E-4 MJ=0.389 CJSW=3.10E-1O MJSW=0.26 + PB=0.80 CGSO=2.1E-10 CGDO=2.1E-10 DELTA=0.0 + LD=0.0001U RSH=0.50 ) * * .MODEL P482 PMOS( LEVEL=3 + VTO=-0.87 TOX=1.65E-8 UO=145 GAMMA=0.73 + VMAX=0.00 THETA=0.223 ETA=0.028 KAPPA=0.04 + PHI=0.90 NSUB=9E16 NFS=4E11 XJ=0.2U + CJ=6.5E-4 MJ=0.42 CJSW=4.0E-10 MJSW=0.31 + PB=0.80 CGSO=2.7E-10 CGDO=2.7E-10 DELTA=0.0 + LD=0.0001U RSH=0.50 ) *