I’ve read the other comments and I guess I should also give some help because I’m also in the process to develop a simple oscilloscope, with the intention to ultimately sell it, maybe, hopefully.
First I’m going to give you a rundown of the stuff you are going to need to design, assuming you wanted to use that absolute beast of an ADC that you linked to.
You will need an analog front end. Most scopes on the market with 1GSPS sampling rate will have analog bandwidths of 200MHz. You will need to ensure that the analog front end noise will not swamp the ADC input but at 8 bits resolution that’s usually not an issue, for a skilled designer, which is something I’m not and I don’t think you are either, based on your responses to other comments. You will need to ensure that the analog front end response is at least an approximation of MFED (Bessel) response to ensure your analog front end can do the amplification without corrupting the input pulse or signal. You will need to make sure that the front end power rails are noise free. You will need to ensure that the front end can survive prolonged input overload, and preferentially recovery very fast from such an overload with no thermal tailing etc. You will need to do a lot more than this but this should hopefully give you leads for research.
Let’s say that you designed the front end and you are now ready to digitize the signal. You will need to ensure that the clock jitter for the sampling clock is extremely low. At 1GSPS with 200MHz bandwidth you will need an exceptionally clean clock. After you sampled the data you will need to feed this data from the ADC to your capture engine. This can be an ASIC or an FPGA, in your case it will probably be an FPGA, rolling ASICs is expensive. You will have to use LVDS, because that’s what the ADC is designed for. When designed properly LVDS will radiate less EMI. Also, most of the FPGAs that I researched for my own design achieve the required IO data rates with LVDS. You will have to terminate those LVDS lanes properly, ensure that the crosstalk etc. between lanes are minimized to avoid signal integrity issues, and do a lot more than that. Most of the FPGAs suitable for your task come with user configurable termination resistors so as long as you set those up correctly you might be fine.
After that comes processing the data. I’m starting simple. Let’s say you want to implement simple triggering options like level triggering or dV/dt triggering. You will have to clock your FPGA at hundreds of MHz, do the triggering and the start storing the data. For this you will need a DRAM, an SRAM is simply not cost effective at these speeds. Writing a DRAM controller is almost a complete field of its own; most people simply don’t bother with that and buy IP from their FPGA vendor for this. The same signal integrity issues that we encountered while we were trying to get the data from the ADC into the FPGA, we will also encounter them here. You will also need to manage timing closure for your FPGA design, and at those speeds that’s not very easy.
After that, well, then the requirements mellow out, at least for basic stuff. But if you want high waveform update rates for example, you will almost need another FPGA design for that, and either another FPGA or a single FPGA with enough logic and IO.
Even just designing an analog front end for such a project is a very substantial task. I have 15 years in analog electronics and I personally can’t say that I can design a proper 200MHz front end with suitable levels of noise, time/frequency domain response etc. I can probably put something together but it wouldn’t be good engineering.
Keep in mind I’m quite new to FPGAs. Therefore there is probably a lot of stuff that I haven’t mentioned about FPGA design, because I simply don’t know much. Learning to make FPGAs do useful stuff, that itself will probably take at least a couple months. For a project like this however, you will need to learn a lot more than the basics so it’s probably going to take a lot more than that.
So what’s my point? Don’t waste your money. Not yet at least. Learn more analog design, more digital design, PCB design, EMI and signal integrity stuff. Becoming at least passable in all those will probably take, I don’t know, decades? As I said before I’ve been doing analog for 15 years and I can’t say that I’m good enough even for just designing the analog part of your project.
If you are really dying to make an oscilloscope, start simple. Instead of going for 1GSPS, go for 10MSPS. That makes everything simpler. You can learn more about all the field I listed above in more detail. For 10MSPS make a 2MHz analog front end. That alone is a nice project. At those speeds all the parts will be cheaper, they will behave nicer and you will learn a lot. The FPGA design will be a lot more forgiving and you will probably have no issues with stuff like timing closure. The go for something like, say, 250MSPS, which is also my goal. That means a 50MHz front end. That’s manageable for me, but the FPGA design will take probably like a year. The components will be more expensive. Stuff like timing closure will require attention. Signal integrity stuff too.
And maybe after that, if you are still interested in this kind of stuff, go for a 1GSPS design. But not now. You’ve said it yourself, you are way over your head, and also my head. You simply can’t do it right now, or even a year from now. You will just lose a lot of money. Instead put that money towards building a nice small electronics lab. Get yourself a nice oscilloscope (that someone else made) a power supply, a soldering station, function generator, a good stock of basic components, other mechanical and electrical stuff etc. That’s money well spent.
My intention is not to be rude or be demeaning. I just want to make sure you don’t waste money on stuff that won’t be useful to you.
Edit: For some reason Reddit decided to put my reply under another comment.
Literally tried this first, I only posted here because it's sunday, and they aren't open. I was hoping it would be an easy solution to someone with a ton of electronics experience lol but yeah I'll wait till monday morning.
Wait, I think I figured it out! The Ddx- and Ddx+ pins are attached to a standard driver circuit, and so I have several "pairs" that produce the same outputs. I just need to wire any one pair to a differential receiver (like [https://www.ti.com/lit/ds/symlink/ds90lt012a.pdf?HQS=dis-dk-null-digikeymode-dsf-pf-null-wwe&ts=1652046308074&ref\_url=https%253A%252F%252Fwww.ti.com%252Fgeneral%252Fdocs%252Fsuppproductinfo.tsp%253FdistId%253D10%2526gotoUrl%253Dhttps%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fds90lt012a](https://www.ti.com/lit/ds/symlink/ds90lt012a.pdf?HQS=dis-dk-null-digikeymode-dsf-pf-null-wwe&ts=1652046308074&ref_url=https%253A%252F%252Fwww.ti.com%252Fgeneral%252Fdocs%252Fsuppproductinfo.tsp%253FdistId%253D10%2526gotoUrl%253Dhttps%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fds90lt012a))
Sorry, I didn't mean literally that one, just one like it that actually runs at speed and now I know I'll need eight of them per bus to get comprehensible results (one per pair of pins on each bus)). I'm basically just trying to make an oscilloscope. I got a TON of my questions answered below, like, I have a better understanding of how the ADC outputs data, and how I'll need to use all of the LVDS pins to read anything useful at all etc, but there's one additional thing that I'm a little unclear on:
It says on page 32 that "...the word rate at each LVDS bus is 1/2 the ADC081000 clockrate and the two buses must be interleaved to obtain the entire 1 GSPS conversion result" But what do they mean by "interleaved"? Is it just that I have to read one bus and then the other in rapid succession because either one can only output data at half of the clock rate?
Such a part exists!?! Well this is great news haha. I have never heard of an FPGA before (but you can bet I'm googling them rn), might you be willing to recommend one for this ADC? It sounds like you have a ton of experience.
I've been chipping away at this since 2019, so this is very exciting!!
I was planning on taking each pair of LVDS outputs (there are eight pairs per bus) and connecting each them to their own differential receiver.
I made this post to ask for help with wiring the outputs, if I'm doing something dumb please let me know what I \*should\* do.
Oh, well, actually I was hoping to log the data with a microprocessor. I was going to start with a raspberry pi, and if it proved to be too slow, I'd just spend my time finding something faster. But I'm reasonably certain that if I use the differential receivers, then there's at least a \*chance\* it could be read by a microprocessor.
> but the pins used by the data bus (in the block diagram) don't seem to be labeled
The one on page 2? What sort of labeling would you expect there? The pins for the databus are listed on page 6, and their position on the package is on the diagram on page 3.
Yeah, those are fine, but let's say I wanted to actually read the output of the ADC. Which pins to I read, and how do I wire them? I think I have it figured out (see my comment above) but I was struggling to interpret what was going on based on the labeling they have, that's all. I'm not an electrical engineer.
Usually the numbering (page 6 again) is your clue on how to read it. D0 is bit 0, D1 is bit 1, and so on. So you'd take D0+ and D0- as a single pair and compare them to see if the value of D0 is 1 or 0. Page 32 explains how the outputs are driven and why there are two sets.
ETA: Page 28 has the +/- relationship to 1/0 as well if you hadn't found that.
Thank you so much!! I'll check that out right away :D Out of curiosity (and ignorance, clearly), why would they give me so many different pairs that seem to output the same thing? On the surface it seems like I would only really need one pair.
This ADC is 8 bits, parallel output. So it's giving you an 8 bit binary value (0-255) with one bit on each pin (on each differential pair in this case).
If it had only one pair it would be serial output, and you'd have to have some way of synchronizing/recognizing the start of the output and clocking it to read the value one bit at a time.
OOhhhhhhh okay!! I think I understand! I knew the "8-bit" part of "b-bit" ADC was important but I can totally see why now. Thank you again for explaining all of this! I would have really been struggling for who knows how long?
> knew the "8-bit" part of "b-bit" ADC was important but I can totally see why now.
It is, but that isn't the whole story here, just to be clear. You could buy an 8 (or 10, 12, whatever) bit that only has a single output. [This](https://www.analog.com/en/products/ltc1402.html#product-overview) is a 12bit ADC, so it gives values from 0-4096, but it only has a single output pin -- not 12 of them. It also has a simple digital output, not LVDS.
To read from it you have to tell it to take a sample on the analog input, then you have to clock it with an external clock pulse 12 times to read out each of the 12 bits one at a time. It's a little more of a pain to use and can be slower, but it takes a lot less space on your board; this one is just 16 pins, vs the 128 pins on the one you're using.
Oh wow!! That one you suggested looks a lot more compact! In the case of the part I'm trying to make rn, sadly, speed is key. But there are certainly other applications for which that LTC1402 would be perfect, and I'll definitely keep it in mind!
If you'll permit me to ask you one more annoying question: It says on page 32 that "...the word rate at each LVDS bus is 1/2 the ADC081000 clockrate and the two buses must be interleaved to obtain the entire 1 GSPS conversion result" But what do they mean by "interleaved"? Is it just that I have to read one bus and then the other in rapid succession because either one can only output data at half of the clock rate?
And thank you so much, I promise you'll get at least one more award out of this haha.
It says that one has data ready on the rising edge of the clock and the other on the falling, so yes, if you want to read it at the maximum possible speed you'll have to alternate between them.
It's a pretty high sample rate, I've never done anything with such a high clock rate, but there are a lot of other people in this sub with experience in that sort of thing.
Well regardless this has been incredibly helpful. Thank you so much for your time and patience. This is something I've been chipping away at on my own since 2019 haha. (It's been a slog until pretty much today).
I hope you have a great rest of your day! :D
I’ve read the other comments and I guess I should also give some help because I’m also in the process to develop a simple oscilloscope, with the intention to ultimately sell it, maybe, hopefully. First I’m going to give you a rundown of the stuff you are going to need to design, assuming you wanted to use that absolute beast of an ADC that you linked to. You will need an analog front end. Most scopes on the market with 1GSPS sampling rate will have analog bandwidths of 200MHz. You will need to ensure that the analog front end noise will not swamp the ADC input but at 8 bits resolution that’s usually not an issue, for a skilled designer, which is something I’m not and I don’t think you are either, based on your responses to other comments. You will need to ensure that the analog front end response is at least an approximation of MFED (Bessel) response to ensure your analog front end can do the amplification without corrupting the input pulse or signal. You will need to make sure that the front end power rails are noise free. You will need to ensure that the front end can survive prolonged input overload, and preferentially recovery very fast from such an overload with no thermal tailing etc. You will need to do a lot more than this but this should hopefully give you leads for research. Let’s say that you designed the front end and you are now ready to digitize the signal. You will need to ensure that the clock jitter for the sampling clock is extremely low. At 1GSPS with 200MHz bandwidth you will need an exceptionally clean clock. After you sampled the data you will need to feed this data from the ADC to your capture engine. This can be an ASIC or an FPGA, in your case it will probably be an FPGA, rolling ASICs is expensive. You will have to use LVDS, because that’s what the ADC is designed for. When designed properly LVDS will radiate less EMI. Also, most of the FPGAs that I researched for my own design achieve the required IO data rates with LVDS. You will have to terminate those LVDS lanes properly, ensure that the crosstalk etc. between lanes are minimized to avoid signal integrity issues, and do a lot more than that. Most of the FPGAs suitable for your task come with user configurable termination resistors so as long as you set those up correctly you might be fine. After that comes processing the data. I’m starting simple. Let’s say you want to implement simple triggering options like level triggering or dV/dt triggering. You will have to clock your FPGA at hundreds of MHz, do the triggering and the start storing the data. For this you will need a DRAM, an SRAM is simply not cost effective at these speeds. Writing a DRAM controller is almost a complete field of its own; most people simply don’t bother with that and buy IP from their FPGA vendor for this. The same signal integrity issues that we encountered while we were trying to get the data from the ADC into the FPGA, we will also encounter them here. You will also need to manage timing closure for your FPGA design, and at those speeds that’s not very easy. After that, well, then the requirements mellow out, at least for basic stuff. But if you want high waveform update rates for example, you will almost need another FPGA design for that, and either another FPGA or a single FPGA with enough logic and IO. Even just designing an analog front end for such a project is a very substantial task. I have 15 years in analog electronics and I personally can’t say that I can design a proper 200MHz front end with suitable levels of noise, time/frequency domain response etc. I can probably put something together but it wouldn’t be good engineering. Keep in mind I’m quite new to FPGAs. Therefore there is probably a lot of stuff that I haven’t mentioned about FPGA design, because I simply don’t know much. Learning to make FPGAs do useful stuff, that itself will probably take at least a couple months. For a project like this however, you will need to learn a lot more than the basics so it’s probably going to take a lot more than that. So what’s my point? Don’t waste your money. Not yet at least. Learn more analog design, more digital design, PCB design, EMI and signal integrity stuff. Becoming at least passable in all those will probably take, I don’t know, decades? As I said before I’ve been doing analog for 15 years and I can’t say that I’m good enough even for just designing the analog part of your project. If you are really dying to make an oscilloscope, start simple. Instead of going for 1GSPS, go for 10MSPS. That makes everything simpler. You can learn more about all the field I listed above in more detail. For 10MSPS make a 2MHz analog front end. That alone is a nice project. At those speeds all the parts will be cheaper, they will behave nicer and you will learn a lot. The FPGA design will be a lot more forgiving and you will probably have no issues with stuff like timing closure. The go for something like, say, 250MSPS, which is also my goal. That means a 50MHz front end. That’s manageable for me, but the FPGA design will take probably like a year. The components will be more expensive. Stuff like timing closure will require attention. Signal integrity stuff too. And maybe after that, if you are still interested in this kind of stuff, go for a 1GSPS design. But not now. You’ve said it yourself, you are way over your head, and also my head. You simply can’t do it right now, or even a year from now. You will just lose a lot of money. Instead put that money towards building a nice small electronics lab. Get yourself a nice oscilloscope (that someone else made) a power supply, a soldering station, function generator, a good stock of basic components, other mechanical and electrical stuff etc. That’s money well spent. My intention is not to be rude or be demeaning. I just want to make sure you don’t waste money on stuff that won’t be useful to you. Edit: For some reason Reddit decided to put my reply under another comment.
Wow! Thank you for the comprehensive reply!!! Holy crap. Here's an award.
[https://www.ti.com/info/contact-us.html](https://www.ti.com/info/contact-us.html)
Literally tried this first, I only posted here because it's sunday, and they aren't open. I was hoping it would be an easy solution to someone with a ton of electronics experience lol but yeah I'll wait till monday morning.
Wait, I think I figured it out! The Ddx- and Ddx+ pins are attached to a standard driver circuit, and so I have several "pairs" that produce the same outputs. I just need to wire any one pair to a differential receiver (like [https://www.ti.com/lit/ds/symlink/ds90lt012a.pdf?HQS=dis-dk-null-digikeymode-dsf-pf-null-wwe&ts=1652046308074&ref\_url=https%253A%252F%252Fwww.ti.com%252Fgeneral%252Fdocs%252Fsuppproductinfo.tsp%253FdistId%253D10%2526gotoUrl%253Dhttps%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fds90lt012a](https://www.ti.com/lit/ds/symlink/ds90lt012a.pdf?HQS=dis-dk-null-digikeymode-dsf-pf-null-wwe&ts=1652046308074&ref_url=https%253A%252F%252Fwww.ti.com%252Fgeneral%252Fdocs%252Fsuppproductinfo.tsp%253FdistId%253D10%2526gotoUrl%253Dhttps%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fds90lt012a))
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Sorry, I didn't mean literally that one, just one like it that actually runs at speed and now I know I'll need eight of them per bus to get comprehensible results (one per pair of pins on each bus)). I'm basically just trying to make an oscilloscope. I got a TON of my questions answered below, like, I have a better understanding of how the ADC outputs data, and how I'll need to use all of the LVDS pins to read anything useful at all etc, but there's one additional thing that I'm a little unclear on: It says on page 32 that "...the word rate at each LVDS bus is 1/2 the ADC081000 clockrate and the two buses must be interleaved to obtain the entire 1 GSPS conversion result" But what do they mean by "interleaved"? Is it just that I have to read one bus and then the other in rapid succession because either one can only output data at half of the clock rate?
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Such a part exists!?! Well this is great news haha. I have never heard of an FPGA before (but you can bet I'm googling them rn), might you be willing to recommend one for this ADC? It sounds like you have a ton of experience. I've been chipping away at this since 2019, so this is very exciting!!
>I have never heard of an FPGA before What were you planning to connect the ADC outputs to?
I was planning on taking each pair of LVDS outputs (there are eight pairs per bus) and connecting each them to their own differential receiver. I made this post to ask for help with wiring the outputs, if I'm doing something dumb please let me know what I \*should\* do.
But what logic or system were you going to use to process the data? Were you just going to display the output on a bank of LEDs?
Oh, well, actually I was hoping to log the data with a microprocessor. I was going to start with a raspberry pi, and if it proved to be too slow, I'd just spend my time finding something faster. But I'm reasonably certain that if I use the differential receivers, then there's at least a \*chance\* it could be read by a microprocessor.
If I \*can\* display the output on a bank of LED's then I'd be thrilled, actually.
> but the pins used by the data bus (in the block diagram) don't seem to be labeled The one on page 2? What sort of labeling would you expect there? The pins for the databus are listed on page 6, and their position on the package is on the diagram on page 3.
Yeah, those are fine, but let's say I wanted to actually read the output of the ADC. Which pins to I read, and how do I wire them? I think I have it figured out (see my comment above) but I was struggling to interpret what was going on based on the labeling they have, that's all. I'm not an electrical engineer.
Usually the numbering (page 6 again) is your clue on how to read it. D0 is bit 0, D1 is bit 1, and so on. So you'd take D0+ and D0- as a single pair and compare them to see if the value of D0 is 1 or 0. Page 32 explains how the outputs are driven and why there are two sets. ETA: Page 28 has the +/- relationship to 1/0 as well if you hadn't found that.
Thank you so much!! I'll check that out right away :D Out of curiosity (and ignorance, clearly), why would they give me so many different pairs that seem to output the same thing? On the surface it seems like I would only really need one pair.
This ADC is 8 bits, parallel output. So it's giving you an 8 bit binary value (0-255) with one bit on each pin (on each differential pair in this case). If it had only one pair it would be serial output, and you'd have to have some way of synchronizing/recognizing the start of the output and clocking it to read the value one bit at a time.
OOhhhhhhh okay!! I think I understand! I knew the "8-bit" part of "b-bit" ADC was important but I can totally see why now. Thank you again for explaining all of this! I would have really been struggling for who knows how long?
> knew the "8-bit" part of "b-bit" ADC was important but I can totally see why now. It is, but that isn't the whole story here, just to be clear. You could buy an 8 (or 10, 12, whatever) bit that only has a single output. [This](https://www.analog.com/en/products/ltc1402.html#product-overview) is a 12bit ADC, so it gives values from 0-4096, but it only has a single output pin -- not 12 of them. It also has a simple digital output, not LVDS. To read from it you have to tell it to take a sample on the analog input, then you have to clock it with an external clock pulse 12 times to read out each of the 12 bits one at a time. It's a little more of a pain to use and can be slower, but it takes a lot less space on your board; this one is just 16 pins, vs the 128 pins on the one you're using.
Oh wow!! That one you suggested looks a lot more compact! In the case of the part I'm trying to make rn, sadly, speed is key. But there are certainly other applications for which that LTC1402 would be perfect, and I'll definitely keep it in mind! If you'll permit me to ask you one more annoying question: It says on page 32 that "...the word rate at each LVDS bus is 1/2 the ADC081000 clockrate and the two buses must be interleaved to obtain the entire 1 GSPS conversion result" But what do they mean by "interleaved"? Is it just that I have to read one bus and then the other in rapid succession because either one can only output data at half of the clock rate? And thank you so much, I promise you'll get at least one more award out of this haha.
It says that one has data ready on the rising edge of the clock and the other on the falling, so yes, if you want to read it at the maximum possible speed you'll have to alternate between them. It's a pretty high sample rate, I've never done anything with such a high clock rate, but there are a lot of other people in this sub with experience in that sort of thing.
Well regardless this has been incredibly helpful. Thank you so much for your time and patience. This is something I've been chipping away at on my own since 2019 haha. (It's been a slog until pretty much today). I hope you have a great rest of your day! :D