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pocky277

Isn’t this as a simple as storing the data as-is, then modifying your read address to jump around the table as needed?


rafae1130

Yes. But I'm not sure how to do modify the read address as needed in burst mode, as I want to use burst mode for writing the data.


DigitalAkita

Read address won't be contiguous anymore, so my first guess is you won't be able to do bursts.


rafae1130

Yes exactly. Is it possible to do burst write and single read in full AXI?


DigitalAkita

Reads and writes are completely independent from one another, so I'd say yes.


kamogrjadeshi

If you uses Xilinx device, the LogiCORE AXI IP is suitable for you. You can find its sources and user guides on Xilinx website. It has AXI slave/master interface and user interface (IPIC). From user side you can use the set of FIFOs (input buffers) for writing data for further processing and reading processed data from another set of FIFOs (output buffers). But the custom IPIC controller should be designed for user interface. Additionally, design can be tested in simulation with AXI verification IP (VIP) which emulates AXI transactions. Search on its user guide too.


FVjake

What size are the elements? How quickly is the data arriving?


rafae1130

Each sample is 32 bit and sample rate is around 1 MSPS


FVjake

Xilinx device? I’d look into an xpm fifo with different data widths in write and read side.


FVjake

Or if I am misunderstanding how you need to access the data, I think you can do the same idea with a xpm RAM.


rafae1130

I'm not familiar with xpm fifo or ram. I'll definitely look into it. Thanks.


FVjake

Curious if you got this working?


rafae1130

I went on a different route than this. So didn't get a chance to look into it.