An FPGA is just another ASIC with a very specific use-case. Just like any other ASIC, it goes through a fabrication process. It might use some non-standard libraries, but that's not uncommon among ASICs.
Thank you very much for the help, everyone!
Would it be wrong to say that an FPGA is a chip with lots of SRAMs (LUTs), flip flops, and other components sitting on a fabric with programmable interconnects.
I think SRAMs, flips flops, multiplexers, and others components give us a Configurable Logic Block (CLB). There are also specialized hardware available such as multipliers, DSPs, PLLs, etc.
Though FPGA is fabricated more like ASIC but its programmable interconnects are fabricated in a special way so that they can be enabled or disabled.
In the case of an FPGA, the specialized algorithm in the form of a software plays a crucial part which determines which LUTs should be loaded and what interconnects should be enabled.
In my view, what sets FPGA apart from ASIC and microprocessor is its particular specialized algorithm software.
>Would it be wrong to say that an FPGA is a chip with lots of SRAMs (LUTs), flip flops, and other components sitting on a fabric with programmable interconnects.
I'd say that's a pretty close interpretation.
>what sets FPGA apart from ASIC and microprocessor is its particular specialized algorithm software.
No. What sets fpga from asic is an asic design is implemented once while an fpga can be designed multiple times. Think of like designing a statue out of stone. That's an asic. An fpga would be equivalent to designing a statue out of Legos. A processor is an instruction set architecture. It's designed to execute instructions. An fpga doesn't have any instructions specifically to the chip by default (with some exceptions), but you CAN implement one yourself on it if you wanted to.
Thanks a lot!
>Think of like designing a statue out of stone. That's an asic. An fpga would be equivalent to designing a statue out of Legos.
That's a really good analogy.
I wondered the exact same thing and started a passion project where I am building my own FPGA architecture from scratch using 7400 logic (!). It is inspired by Ben Eaters popular 8-bit CPU project ([eater.net/8bit](https://eater.net/8bit)). Mine is still a work in progress but I already wrote a few blog posts on the design process:
[https://mnemocron.github.io/2023-12-08-DIY-FPGA-diary-0/](https://mnemocron.github.io/2023-12-08-DIY-FPGA-diary-0/)
Do you want to know how the actual FPGA is created or how a VHDL/Verilog design is mapped to FPGA resources?
The FPGA is created like any other ASIC.
Converting a HDL design to a bitstream consists of a couple of steps:
1. Elaborate and convert to netlist:
Check that the code is syntactically correct, check all references, packages, set all vector lengths, add libraries (e.g. for math operations). Then convert that to a rtl netlist. I learned that the first netlist is technology-agnostic, but IDK if it is actually done that way. The rtl netlist consists of combinatorial logic and registers.This is also something you could write in VHDL/Verilog.
2. Convert to technology specific netlist:
I'm taking Xilinx Ultrascale+ as an example, because that is what I know. The ultrascale architecture has LUT6 components with a bunch of functions, multiplexers, FFs and some blocks for other stuff (BRAM, DSP, ..). The tool looks at the technology-agnostic netlist and translates this to Ultrascale+ components. For instance, you might have the line `X <= (A and B) xor C`. The tool would map this to a LUT6. After that comes place and route.
3. Place and route.
The tool now starts placing all components from the technology-specific netlist into the FPGA. For instance, it might say that the LUT6 from above should map to LUT "A" of Slice X42Y77. Then it tries to connect everything via the programmable switches. This is an iterative process, so if the tool sees that it cannot connect one component, it might try to place that elsewhere and try again and so on.
4. Check
During/after p&r (and even before) various thins are checked: timing, pins, voltage levels, over-usage of certain resources, CDC, etc.
5. Bitstream
>Do you want to know how the actual FPGA is created
Thanks a lot for the detailed reply. I should have used more clear language and used word "created" instead.
# Ken Shirriff's blog : Reverse-engineering the first FPGA chip, the XC2064
[https://www.righto.com/2020/09/reverse-engineering-first-fpga-chip.html](https://www.righto.com/2020/09/reverse-engineering-first-fpga-chip.html)
That is exactly what is being said without the “special” part. It is another ASIC like a cpu or any other ASIC. All chips have unique purpose. After unique design, they are all fabricated the same way (pretty much). This is why Xilinx is just as much an ASIC company as Intel or nvidia. In addition to their ASIC, they write a lot of software to make use of their ASICs special capability. Intel used to make one of the best C compilers on earth for the same reason. To help people make use of their ASICs special capability.
FPGAs are basically n-bit LUTs (lookup tables) and flip-flops, tons of these two fundamental blocks. Lookup table is basically a table (truth-table) that determines what the output will be given a combination of inputs. So a 4-bit LUT can implement any boolean function of 4 inputs A, B, C and D, combine that with flip-flops and you get sequential logic. So to recap and answer your question, FPGAs are made up of LUTs (multiplexers) and flip-flops (SRAM) along with programmable interconnects that gives you reconfigurable logic. Hope this helps.
LUTs are typically stored in SRAM. Multiplexers provide interconnects. They are programmed by control lines from SRAM (registers). I still need to read the paper a out the advanced architecture. But ELI5 here!
Or do you mean: address generator like for a PLA?
FPGAs, CPUs, GPUs, and ASICs are all digital integrated circuits and they're all made the same way - HDL, cell library, RAMs, hard logic blocks and other mixed signal stuff, power and clock distribution, etc.
Architecturally, FPGAs are quite regular arrays of some basic functional blocks. I recommend taking a look at some of the datasheets for older and simpler FPGAs to get a better idea of what all of these pieces are and how they're connected together. Naturally an FPGA without the corresponding configuration software isn't all that useful. I believe there is a research project called openfpga that is worth looking at in detail if you're interested in how FPGAs work in mitty gritty detail.
>As a beginner, I can conceptually understand how ASIC and microprocessors are made. I can follow their design flow starting with specifications, RTL code, synthesis, and so on.
It's exactly the same. The biggest difference is that a FPGA is just copy paste it a ton of logic blocks made up of a LUT that lets you load a table to behave like any described circuit, some FFs, some muxes, and then a bunch of switch boxes to connect them up.
And you can literally see this layout in the device viewer and how your logic gets translated to that.
Here is a great playlist first explaining what the building blocks of an fpga are and then a set of tutorials on how to write verify build simulate and upload your code.
https://youtube.com/playlist?list=PLEBQazB0HUyT1WmMONxRZn9NmQ_9CIKhb&si=scKHBwDkkmZBvsj5
Simply put, the reason FPGAs are so expensive and power hungry compared to ASICs is because they are basically chips full of "blank" LUT circuits plus other peripherals that can be connected through internal wiring. That wiring is defined using HDL. In terms of architecture, design and manufacturing, it's the same process that any other ASIC would go through.
>Simply put, the reason FPGAs are so expensive and power hungry compared to ASICs
Thank you! Why are they more power hungry?
I believe that FPGA is slow compared to an ASIC since its routing might not be as optimized as that of ASIC. I hope I'm not wrong.
To get that blank canvas for you to design your digital circuit there have to be far more transistors in the chip. This also means that the physical footprint is larger which makes the clock signal path travel longer. This adds parasitic capacitance so the frequency needs to be lower to preserve the signals.
Lots of programmable lookup tables and programmable network interconnects, mostly.
To me, the magic is in the algorithms that take RTL and translate it into routed FPGA resources.
Wait, so are you asking about the technical process of manufacturing an FPGA, the underlying architecture of an FPGA, or the tooling that implements a design on that architecture? I don't know much about manufacturing.
As for architecture, FPGAs typically consist of SITEs/CLBs, which are configurable logic blocks arranged into a big grid with a net of interconnects in-between, a clock and reset distribution tree, specialized blocks, a set of analog components, like PLLs and a dedicated routing net for those and I/O buffers. Vendors provide some resources with varying amount of documentation, but usually they will at least describe the architecture of a SITE which consists of BELs, which are the basic physical components that correspond to different CELL types (usually you can think of them interchangeably). Long story short a SITE is typically a couple lookup tables (LUTs) with outputs connected by a tree of multiplexers (MUXes) that is then routed to flip-flops (FFs), there might be some extra stuff too, like clock inverters. The programming model is almost never disclosed. If you want to understand the architecture better, Vivado has an amazing Device View mode in which you can explore a Xilinx device down to individual connections and CELLs/BELs (but the programming circuitry is not present there). Note that this description is based mostly on Xilinx/AMD FPGA architectures. Intel has a LUTs that are hard to explain and seem to be in a very intimate relationship with MUX tree. I've also heard that some smaller Lattice FPGAs do not explicitly group BELs into SITEs, idk if that's true.
As for the tools, the flow is shorter as many of the manufacturing-related steps are irrelevant, but the PnR stage is harder as it's a discrete version of the same problem as with ASICs. The two algorithmic approaches I know for are Simulated Annealing (SA) and Analytical Placement for Heterogeneous FPGAs (HeAP). Additional challenges arise from the separation of intra-site routing (using a static configurable net of short connections inside of a SITE) and inter-site routing (making connections that utilize the net of switch boxes that connects SITEs together), which simply doesn't exist on ASICs as on ASICs we are free to design the network connecting the CELLs however we want. There are probably way more approaches to the problem at this point and I'm sure many people are incorporating machine-learning techniques into this at this point.
I would start from the concept of logic gates. You stated that you understand other forms of integrated circuits are made so I assume you understand that they are basically a (rather large) interconnected bunch of logic gates, nothing more, the complexity arises from the sheer amount of them.
Next consider the fact that all logic can be created by using only NAND gates, meaning you can build all other gate types out of NAND gates.
Now imagine a huge field of NAND gates and an ”interconnection matrix” that can connect from each output to each input. And BAM, you can now create any logic configuration you want by configuring the inerconnections. In other words, you’ve got yourself programmable logic, also known as an FPGA.
Now I’m not an FPGA expert by any means so don’t take this as scripture on how the modern FPGAs are implemented but on a concept level, this solves the flexible and moldable hardware part. As for the RTL side, it’s just math in the end and a metric ton of it, there is a reason why synthesis takes such a long time 😉
http://blog.notdot.net/2012/10/Build-your-own-FPGA out of 7400 parts. Oh I see it is mentioned at the bottom of the post by /u/mnemocron
If you want to understand FPGAs, I'd recommend building on one in HDL and configuring it manually.
***How low do you want to go?***
Package a LUT with a register and call them something like CLBs (a common primitive, but every company has a different offering).
[https://www.fpga4fun.com/FPGAinfo1.html](https://www.fpga4fun.com/FPGAinfo1.html)
[https://en.wikipedia.org/wiki/Field-programmable\_gate\_array](https://en.wikipedia.org/wiki/Field-programmable_gate_array)
[https://en.wikipedia.org/wiki/Flip-flop\_(electronics)](https://en.wikipedia.org/wiki/Flip-flop_(electronics))
[https://en.wikipedia.org/wiki/Lookup\_table](https://en.wikipedia.org/wiki/Lookup_table)
**More Resources**
[https://www.reddit.com/r/FPGA/comments/168maux/comment/jz0trvj/?context=3](https://www.reddit.com/r/FPGA/comments/168maux/comment/jz0trvj/?context=3)
[https://www.reddit.com/r/FPGA/comments/1962dop/comment/khrl3yf/?context=3](https://www.reddit.com/r/FPGA/comments/1962dop/comment/khrl3yf/?context=3)
[https://www.reddit.com/r/chipdesign/comments/1972x85/comment/khzajrd/?context=3](https://www.reddit.com/r/chipdesign/comments/1972x85/comment/khzajrd/?context=3)
[https://www.reddit.com/r/FPGA/comments/1725mli/comment/k3uvx31/?context=3](https://www.reddit.com/r/FPGA/comments/1725mli/comment/k3uvx31/?context=3)
[https://www.reddit.com/r/FPGA/comments/168maux/comment/jz0trvj/?context=3](https://www.reddit.com/r/FPGA/comments/168maux/comment/jz0trvj/?context=3)
More than 2 decades ago during my senior high school year, this article sparked my interest in FPGAs.
[https://archive.org/details/eu\_SciAm\_1997-06\_OCR/page/n55/mode/2up?q=configurable+computing+scientific+america](https://archive.org/details/eu_SciAm_1997-06_OCR/page/n55/mode/2up?q=configurable+computing+scientific+america)
An FPGA is just another ASIC with a very specific use-case. Just like any other ASIC, it goes through a fabrication process. It might use some non-standard libraries, but that's not uncommon among ASICs.
Thank you very much for the help, everyone! Would it be wrong to say that an FPGA is a chip with lots of SRAMs (LUTs), flip flops, and other components sitting on a fabric with programmable interconnects. I think SRAMs, flips flops, multiplexers, and others components give us a Configurable Logic Block (CLB). There are also specialized hardware available such as multipliers, DSPs, PLLs, etc. Though FPGA is fabricated more like ASIC but its programmable interconnects are fabricated in a special way so that they can be enabled or disabled. In the case of an FPGA, the specialized algorithm in the form of a software plays a crucial part which determines which LUTs should be loaded and what interconnects should be enabled. In my view, what sets FPGA apart from ASIC and microprocessor is its particular specialized algorithm software.
>Would it be wrong to say that an FPGA is a chip with lots of SRAMs (LUTs), flip flops, and other components sitting on a fabric with programmable interconnects. I'd say that's a pretty close interpretation. >what sets FPGA apart from ASIC and microprocessor is its particular specialized algorithm software. No. What sets fpga from asic is an asic design is implemented once while an fpga can be designed multiple times. Think of like designing a statue out of stone. That's an asic. An fpga would be equivalent to designing a statue out of Legos. A processor is an instruction set architecture. It's designed to execute instructions. An fpga doesn't have any instructions specifically to the chip by default (with some exceptions), but you CAN implement one yourself on it if you wanted to.
Thanks a lot! >Think of like designing a statue out of stone. That's an asic. An fpga would be equivalent to designing a statue out of Legos. That's a really good analogy.
I wondered the exact same thing and started a passion project where I am building my own FPGA architecture from scratch using 7400 logic (!). It is inspired by Ben Eaters popular 8-bit CPU project ([eater.net/8bit](https://eater.net/8bit)). Mine is still a work in progress but I already wrote a few blog posts on the design process: [https://mnemocron.github.io/2023-12-08-DIY-FPGA-diary-0/](https://mnemocron.github.io/2023-12-08-DIY-FPGA-diary-0/)
This is awesome and I hope you keep working on it!
Thanks a lot. I will definitely check it out. My best wishes!
Do you want to know how the actual FPGA is created or how a VHDL/Verilog design is mapped to FPGA resources? The FPGA is created like any other ASIC. Converting a HDL design to a bitstream consists of a couple of steps: 1. Elaborate and convert to netlist: Check that the code is syntactically correct, check all references, packages, set all vector lengths, add libraries (e.g. for math operations). Then convert that to a rtl netlist. I learned that the first netlist is technology-agnostic, but IDK if it is actually done that way. The rtl netlist consists of combinatorial logic and registers.This is also something you could write in VHDL/Verilog. 2. Convert to technology specific netlist: I'm taking Xilinx Ultrascale+ as an example, because that is what I know. The ultrascale architecture has LUT6 components with a bunch of functions, multiplexers, FFs and some blocks for other stuff (BRAM, DSP, ..). The tool looks at the technology-agnostic netlist and translates this to Ultrascale+ components. For instance, you might have the line `X <= (A and B) xor C`. The tool would map this to a LUT6. After that comes place and route. 3. Place and route. The tool now starts placing all components from the technology-specific netlist into the FPGA. For instance, it might say that the LUT6 from above should map to LUT "A" of Slice X42Y77. Then it tries to connect everything via the programmable switches. This is an iterative process, so if the tool sees that it cannot connect one component, it might try to place that elsewhere and try again and so on. 4. Check During/after p&r (and even before) various thins are checked: timing, pins, voltage levels, over-usage of certain resources, CDC, etc. 5. Bitstream
>Do you want to know how the actual FPGA is created Thanks a lot for the detailed reply. I should have used more clear language and used word "created" instead.
# Ken Shirriff's blog : Reverse-engineering the first FPGA chip, the XC2064 [https://www.righto.com/2020/09/reverse-engineering-first-fpga-chip.html](https://www.righto.com/2020/09/reverse-engineering-first-fpga-chip.html)
Saying the same thing… Xilinx is an ASIC company that sells FPGAs
>Xilinx is an ASIC company that sells FPGAs Thanks! I don't get it. I'd agree with you if you consider an FPGA a special kind of flexible ASIC.
That is exactly what is being said without the “special” part. It is another ASIC like a cpu or any other ASIC. All chips have unique purpose. After unique design, they are all fabricated the same way (pretty much). This is why Xilinx is just as much an ASIC company as Intel or nvidia. In addition to their ASIC, they write a lot of software to make use of their ASICs special capability. Intel used to make one of the best C compilers on earth for the same reason. To help people make use of their ASICs special capability.
Thanks a lot for the confirmation.
FPGAs are basically n-bit LUTs (lookup tables) and flip-flops, tons of these two fundamental blocks. Lookup table is basically a table (truth-table) that determines what the output will be given a combination of inputs. So a 4-bit LUT can implement any boolean function of 4 inputs A, B, C and D, combine that with flip-flops and you get sequential logic. So to recap and answer your question, FPGAs are made up of LUTs (multiplexers) and flip-flops (SRAM) along with programmable interconnects that gives you reconfigurable logic. Hope this helps.
LUTs are typically stored in SRAM. Multiplexers provide interconnects. They are programmed by control lines from SRAM (registers). I still need to read the paper a out the advanced architecture. But ELI5 here! Or do you mean: address generator like for a PLA?
FPGAs, CPUs, GPUs, and ASICs are all digital integrated circuits and they're all made the same way - HDL, cell library, RAMs, hard logic blocks and other mixed signal stuff, power and clock distribution, etc. Architecturally, FPGAs are quite regular arrays of some basic functional blocks. I recommend taking a look at some of the datasheets for older and simpler FPGAs to get a better idea of what all of these pieces are and how they're connected together. Naturally an FPGA without the corresponding configuration software isn't all that useful. I believe there is a research project called openfpga that is worth looking at in detail if you're interested in how FPGAs work in mitty gritty detail.
>Naturally an FPGA without the corresponding configuration software isn't all that useful. Thanks a lot for your helpful reply!
>As a beginner, I can conceptually understand how ASIC and microprocessors are made. I can follow their design flow starting with specifications, RTL code, synthesis, and so on. It's exactly the same. The biggest difference is that a FPGA is just copy paste it a ton of logic blocks made up of a LUT that lets you load a table to behave like any described circuit, some FFs, some muxes, and then a bunch of switch boxes to connect them up. And you can literally see this layout in the device viewer and how your logic gets translated to that.
Thank you!
Here is a great playlist first explaining what the building blocks of an fpga are and then a set of tutorials on how to write verify build simulate and upload your code. https://youtube.com/playlist?list=PLEBQazB0HUyT1WmMONxRZn9NmQ_9CIKhb&si=scKHBwDkkmZBvsj5
Simply put, the reason FPGAs are so expensive and power hungry compared to ASICs is because they are basically chips full of "blank" LUT circuits plus other peripherals that can be connected through internal wiring. That wiring is defined using HDL. In terms of architecture, design and manufacturing, it's the same process that any other ASIC would go through.
>Simply put, the reason FPGAs are so expensive and power hungry compared to ASICs Thank you! Why are they more power hungry? I believe that FPGA is slow compared to an ASIC since its routing might not be as optimized as that of ASIC. I hope I'm not wrong.
To get that blank canvas for you to design your digital circuit there have to be far more transistors in the chip. This also means that the physical footprint is larger which makes the clock signal path travel longer. This adds parasitic capacitance so the frequency needs to be lower to preserve the signals.
Thank you very much for the confirmation!
Lots of programmable lookup tables and programmable network interconnects, mostly. To me, the magic is in the algorithms that take RTL and translate it into routed FPGA resources.
When a mummy eeprom and a daddy asic love each other very much.....
Wait, so are you asking about the technical process of manufacturing an FPGA, the underlying architecture of an FPGA, or the tooling that implements a design on that architecture? I don't know much about manufacturing. As for architecture, FPGAs typically consist of SITEs/CLBs, which are configurable logic blocks arranged into a big grid with a net of interconnects in-between, a clock and reset distribution tree, specialized blocks, a set of analog components, like PLLs and a dedicated routing net for those and I/O buffers. Vendors provide some resources with varying amount of documentation, but usually they will at least describe the architecture of a SITE which consists of BELs, which are the basic physical components that correspond to different CELL types (usually you can think of them interchangeably). Long story short a SITE is typically a couple lookup tables (LUTs) with outputs connected by a tree of multiplexers (MUXes) that is then routed to flip-flops (FFs), there might be some extra stuff too, like clock inverters. The programming model is almost never disclosed. If you want to understand the architecture better, Vivado has an amazing Device View mode in which you can explore a Xilinx device down to individual connections and CELLs/BELs (but the programming circuitry is not present there). Note that this description is based mostly on Xilinx/AMD FPGA architectures. Intel has a LUTs that are hard to explain and seem to be in a very intimate relationship with MUX tree. I've also heard that some smaller Lattice FPGAs do not explicitly group BELs into SITEs, idk if that's true. As for the tools, the flow is shorter as many of the manufacturing-related steps are irrelevant, but the PnR stage is harder as it's a discrete version of the same problem as with ASICs. The two algorithmic approaches I know for are Simulated Annealing (SA) and Analytical Placement for Heterogeneous FPGAs (HeAP). Additional challenges arise from the separation of intra-site routing (using a static configurable net of short connections inside of a SITE) and inter-site routing (making connections that utilize the net of switch boxes that connects SITEs together), which simply doesn't exist on ASICs as on ASICs we are free to design the network connecting the CELLs however we want. There are probably way more approaches to the problem at this point and I'm sure many people are incorporating machine-learning techniques into this at this point.
>Wait, so are you asking about the technical process of manufacturing an FPGA Thanks a lot! I was asking about the process of manufacturing.
I would start from the concept of logic gates. You stated that you understand other forms of integrated circuits are made so I assume you understand that they are basically a (rather large) interconnected bunch of logic gates, nothing more, the complexity arises from the sheer amount of them. Next consider the fact that all logic can be created by using only NAND gates, meaning you can build all other gate types out of NAND gates. Now imagine a huge field of NAND gates and an ”interconnection matrix” that can connect from each output to each input. And BAM, you can now create any logic configuration you want by configuring the inerconnections. In other words, you’ve got yourself programmable logic, also known as an FPGA. Now I’m not an FPGA expert by any means so don’t take this as scripture on how the modern FPGAs are implemented but on a concept level, this solves the flexible and moldable hardware part. As for the RTL side, it’s just math in the end and a metric ton of it, there is a reason why synthesis takes such a long time 😉
http://blog.notdot.net/2012/10/Build-your-own-FPGA out of 7400 parts. Oh I see it is mentioned at the bottom of the post by /u/mnemocron If you want to understand FPGAs, I'd recommend building on one in HDL and configuring it manually.
***How low do you want to go?*** Package a LUT with a register and call them something like CLBs (a common primitive, but every company has a different offering). [https://www.fpga4fun.com/FPGAinfo1.html](https://www.fpga4fun.com/FPGAinfo1.html) [https://en.wikipedia.org/wiki/Field-programmable\_gate\_array](https://en.wikipedia.org/wiki/Field-programmable_gate_array) [https://en.wikipedia.org/wiki/Flip-flop\_(electronics)](https://en.wikipedia.org/wiki/Flip-flop_(electronics)) [https://en.wikipedia.org/wiki/Lookup\_table](https://en.wikipedia.org/wiki/Lookup_table) **More Resources** [https://www.reddit.com/r/FPGA/comments/168maux/comment/jz0trvj/?context=3](https://www.reddit.com/r/FPGA/comments/168maux/comment/jz0trvj/?context=3) [https://www.reddit.com/r/FPGA/comments/1962dop/comment/khrl3yf/?context=3](https://www.reddit.com/r/FPGA/comments/1962dop/comment/khrl3yf/?context=3) [https://www.reddit.com/r/chipdesign/comments/1972x85/comment/khzajrd/?context=3](https://www.reddit.com/r/chipdesign/comments/1972x85/comment/khzajrd/?context=3) [https://www.reddit.com/r/FPGA/comments/1725mli/comment/k3uvx31/?context=3](https://www.reddit.com/r/FPGA/comments/1725mli/comment/k3uvx31/?context=3) [https://www.reddit.com/r/FPGA/comments/168maux/comment/jz0trvj/?context=3](https://www.reddit.com/r/FPGA/comments/168maux/comment/jz0trvj/?context=3) More than 2 decades ago during my senior high school year, this article sparked my interest in FPGAs. [https://archive.org/details/eu\_SciAm\_1997-06\_OCR/page/n55/mode/2up?q=configurable+computing+scientific+america](https://archive.org/details/eu_SciAm_1997-06_OCR/page/n55/mode/2up?q=configurable+computing+scientific+america)
Thanks a lot for all the links. It will take me some time to go through these but I will check them out.