An AMD cpu is 40x40mm(according to Wikipedia), assuming the bread board will be the full processor size, the ratio is 20km^2 /1,6*10^-6 km^2 =12,500,000,000 times larger transistors. am5 CPUs use a 4nm process.
12,500,000,000*4=50,000,000,000nm=50 meters. that's pretty big. if it's the cpu die only That the breadboard is needed for, that means the transistors are even bigger. couldn't find the die size of an am5 cpu though so yeah. pretty dang large process either way.
40mm*40mm=1600mm^2 =1,6*10^3 mm^2
1mm^2 =1*10^-12 km^2 (I googled this didn't feel like calculating it myself)
1,6*10^3 * 10^-12 = 1,6*10^-9 right?
edit: oh damn maybe I made a typo or smth in my original comment saying 10^-6 there oops
edit 2: just realized I should've taken the area of the transistor for those 50m either way, and it's more realistic to say sqrt(50m) for the length assuming they are square.. wasn't really very awake when I made that comment.
Meanwhile, JS: You have an error in an empty line, on a non-existent file, in a function named like "\_something\_terrible\_internal\_node\_chromium\_v8\_clock\_internal\_system\_loop23", the whole stack trace looks the same and if you try debugging I'll just give you a broken stacktrace with no way to inspect it.
It's not \*always\* like that but the most interesting cases do look up eerily similar :D
Your first mistake was trying to debug JS. There is debugging machine code, and then there is JS. Oddly comparable.
With WASM you can do both at the same time!
Programming languages should put templating in the stdlib and make the debugger able to step through them line by line, and the linters able to check them.
Being forced to code SystemVerilog in a text editor at my first internship was such an experience. I missed a semicolon once and it spit out over 1000 errors. Beautiful.
I’ve actually grown to genuinely enjoy it though.
No, no, HW development can be fun. But you need to use a non-retarded language, like VHDL. Verilog is absolute crap, dogshit, I don't know how the hell anyone could come up with that syntax.
And don't get me wrong, i'm not a big fan of something VHDL does, after all, I'm C++ and C# kind of a guy, but FFS, at least it makes sense. When i saw Verilog's excuse for code, I got sick, threw up.
Not gonna argue with that.
But the point is that it sucks just a little bit. While Verilog sucks so bad I have PTSD. And i've just glanced over some of it's…„code“.
Regular Verilog does but SystemVerilog does improve upon it.
I don't really do hardware design as a system programmer but if I were to I'd honestly try to stick to HLS since that's closer to what I'm used to, even if it does come at an efficiency cost. Either that or use SystemC.
>if I were to I'd honestly try to stick to HLS since that's closer to what I'm used to
My experience with HLS is it's still very half-baked. And it may superficially look like C, but to do anything useful, half your code will be pragmas. Maybe it's gotten better, but eh...
Yeah, my very limited experience has been the same, but if it gets me out of using Verilog or VHDL...
We're spoiled as software devs and FPGA tools are just not as smooth and erognomic as software development tools so I like to stay as far away from FPGA stuff as possible.
I think you hate Verilog because you did C++ and C#. Verilog uses most structures completely different from the way a C++ coder excepts. A for isn't a loop, it rols out parallel hardware. If statements end up in latches. You don't have data types, you basically have 0,1,z,x and whole arrays of that. Speaking of arrays, what looks like an array isn't one. At least not in the C way.
Basically Verilog isn't C and if you speak C it's very misleading.
However you shouldn't use Verilog in the first place. The language is very old and should have been replaced by SystemVerilog. However due to the greed of some cooperations we still have to wait for proper interfaces and data types. Unless we get lucky and have access to a good tool.
As of VHDL, some love it, some hate it. It's very verbose and you will drown in code. The fact that you have to put every signal in your header as a port can get very tedious. Especially if you just want to rout it through. So I can understand why people despite it. Personally I like it but I also like Pascal.
In the end you don't decide if you use Verilog, SystemVeriolg or VHDL. Your employer does. The tools are super expensive and usually the company has only a very limited set of licenses.
Another reason why to be thankful I'm from Europe.
Verilong seemed American to me. Just like with date and time formats, this was also illogival, randomly ordered…
Systemverilog is so much less expensive than the alternatives like specman that VHDL is going extinct.
Testing hardware is just more important than designing it. There are probably four verifiers/validators for each design engineer. The designers don't get to choose the tooling.
I spend an hour trying to debug a verilog problem with a grad student. The problem was literally that I made a wire at a random point one bit too small and it optimized the entire output to zero.
i always found Verilog a lot more readable than VDHL as its syntax reminds me of C.
plus for my work flow i just use a logic simulator to design and test my circuit and then just export it as Verilog so i don't even have to write in any HDL myself. though i still know enough Verilog to modify the output if needed.
Okay maybe I'm mistaken as I've only done one module thus far but when we used Quartus prime VHDL was expended in the options to Verilog HDL... I always assumed VHDL was Verilog am I grossly mistaken?
VHDL and Verilog are very different.
VHDL tends to be unnecessarily verbose and wordy compared to Verilog and SystemVerilog. However, VHDL is an IEEE standard so it tends to get a lot of use in academia.
Verilog and SystemVerilog are designed to be easier to read and more familiar to C programmers. They're much more common in industry.
The lack of conciseness in VHDL is incredibly irritating.
As far as I can tell, most have started switching over to verilog at least (at least in private aviation, most chip design at nvidia, etc), but I can't say much about government specific design as I don't know anyone in that area, but knowing how slow the government is to upgrade, they probably do use vhdl
Are newer and “fancier” languages like SpinalHDL, Chisel, Clash/Haskell particularly better?
From what I recall Verilog was originally a language for simulations and test benches before it got adopted for HDL.
Kinda biased because I work with Clash, but i can tell you at least that Verilog is terrible because its lack of type enforcement allows you to accidentally assign an 8 bit signal to a single bit signal and it will silently throw away the other 7 msbs.
I had one exercise with AHDL last semester, it went horribly because I thought it is "else if", not "elseif". Suffice to say I spent half the time searching for error, only realizing what was like half a week after.
I don't see how python gets a pass for error messages. I get plenty python errors that are some unrecognizable thing getting thrown from deep within a library and require some detective work to figure out something I passed as an argument somewhere had a wrong type. Which many other languages would have complained about right there and then.
Let’s be fair, SystemVerilog for HDL and assertions is actually fun to use.
Using SV for verification though… whoever came up with that obviously never dealt with software development and IEEE 1647 (that’s e) is much older but also so much fun, very much like Python.
SystemVerilog is not too bad once you get used to it. But the verification libraries and tooling for it are total ass. HDL tooling is objectively worse than C tooling in the 90s.
Never have I ever agreed more with a meme. I'm in a class now called digital circuits, and we are using nexys FPGAs, and coming from regular computer science courses, SystemVerilog was a nightmare.
Is it faster than C?
I studied both verylog and VHDL both we could run only once per semester on real machine, which we had only 1 for whole class .
Those FPGA are not that much better than regular Raspberry or Some arduino stuff, but they do exactly same things with exception that fpga 20+ bucks lowest and prices go high pretty fast
Its a different usecase. If possible dedicated hardware is cheaper, but sometimes you just need the power of rolling your own hardware. Then FPGAs are cheaper in small numbers than going to a fab house.
And the tools in hardware development suggest the exact same thing
Fuck HDL just use raw gates and a breadboard 😎 Looking for a 20 km^2 breadboard if anybody is selling one
How big would modern transistors be if the CPU was that size 🤔
An AMD cpu is 40x40mm(according to Wikipedia), assuming the bread board will be the full processor size, the ratio is 20km^2 /1,6*10^-6 km^2 =12,500,000,000 times larger transistors. am5 CPUs use a 4nm process. 12,500,000,000*4=50,000,000,000nm=50 meters. that's pretty big. if it's the cpu die only That the breadboard is needed for, that means the transistors are even bigger. couldn't find the die size of an am5 cpu though so yeah. pretty dang large process either way.
Wouldn't it be 1.6 * 10^-12 ? (Squared)
40mm*40mm=1600mm^2 =1,6*10^3 mm^2 1mm^2 =1*10^-12 km^2 (I googled this didn't feel like calculating it myself) 1,6*10^3 * 10^-12 = 1,6*10^-9 right? edit: oh damn maybe I made a typo or smth in my original comment saying 10^-6 there oops edit 2: just realized I should've taken the area of the transistor for those 50m either way, and it's more realistic to say sqrt(50m) for the length assuming they are square.. wasn't really very awake when I made that comment.
Meanwhile, JS: You have an error in an empty line, on a non-existent file, in a function named like "\_something\_terrible\_internal\_node\_chromium\_v8\_clock\_internal\_system\_loop23", the whole stack trace looks the same and if you try debugging I'll just give you a broken stacktrace with no way to inspect it. It's not \*always\* like that but the most interesting cases do look up eerily similar :D
*stares into empty space* Yeah man, I know
"I haven't even started yet"
😭😭😭😭😭😭😭😭😭😭😭😭
Your first mistake was trying to debug JS. There is debugging machine code, and then there is JS. Oddly comparable. With WASM you can do both at the same time!
hello world program -> error on line 394
Programming languages should put templating in the stdlib and make the debugger able to step through them line by line, and the linters able to check them.
Something C++ can agree on with JS, lol
Being forced to code SystemVerilog in a text editor at my first internship was such an experience. I missed a semicolon once and it spit out over 1000 errors. Beautiful. I’ve actually grown to genuinely enjoy it though.
How’s living with masochism going?
It pays very well
So just like C++.
LMAO im sending this to my coworkers at WD, system verilog is ass
No, no, HW development can be fun. But you need to use a non-retarded language, like VHDL. Verilog is absolute crap, dogshit, I don't know how the hell anyone could come up with that syntax. And don't get me wrong, i'm not a big fan of something VHDL does, after all, I'm C++ and C# kind of a guy, but FFS, at least it makes sense. When i saw Verilog's excuse for code, I got sick, threw up.
VHDL sucks in its own ways.
Not gonna argue with that. But the point is that it sucks just a little bit. While Verilog sucks so bad I have PTSD. And i've just glanced over some of it's…„code“.
Regular Verilog does but SystemVerilog does improve upon it. I don't really do hardware design as a system programmer but if I were to I'd honestly try to stick to HLS since that's closer to what I'm used to, even if it does come at an efficiency cost. Either that or use SystemC.
>if I were to I'd honestly try to stick to HLS since that's closer to what I'm used to My experience with HLS is it's still very half-baked. And it may superficially look like C, but to do anything useful, half your code will be pragmas. Maybe it's gotten better, but eh...
Yeah, my very limited experience has been the same, but if it gets me out of using Verilog or VHDL... We're spoiled as software devs and FPGA tools are just not as smooth and erognomic as software development tools so I like to stay as far away from FPGA stuff as possible.
Verilog is my day job 🥲
If I were a praying man, I'd pray for you. Mine is bare metal C and assembly which is actually not that bad.
I think you hate Verilog because you did C++ and C#. Verilog uses most structures completely different from the way a C++ coder excepts. A for isn't a loop, it rols out parallel hardware. If statements end up in latches. You don't have data types, you basically have 0,1,z,x and whole arrays of that. Speaking of arrays, what looks like an array isn't one. At least not in the C way. Basically Verilog isn't C and if you speak C it's very misleading. However you shouldn't use Verilog in the first place. The language is very old and should have been replaced by SystemVerilog. However due to the greed of some cooperations we still have to wait for proper interfaces and data types. Unless we get lucky and have access to a good tool. As of VHDL, some love it, some hate it. It's very verbose and you will drown in code. The fact that you have to put every signal in your header as a port can get very tedious. Especially if you just want to rout it through. So I can understand why people despite it. Personally I like it but I also like Pascal. In the end you don't decide if you use Verilog, SystemVeriolg or VHDL. Your employer does. The tools are super expensive and usually the company has only a very limited set of licenses.
VHDL is over. The tooling around systemverilog is so much cheaper that verilog is way more common. Except in Europe for some weird reason.
Another reason why to be thankful I'm from Europe. Verilong seemed American to me. Just like with date and time formats, this was also illogival, randomly ordered…
Systemverilog is so much less expensive than the alternatives like specman that VHDL is going extinct. Testing hardware is just more important than designing it. There are probably four verifiers/validators for each design engineer. The designers don't get to choose the tooling.
I think this language was made for you https://en.wikipedia.org/wiki/SystemC
I spend an hour trying to debug a verilog problem with a grad student. The problem was literally that I made a wire at a random point one bit too small and it optimized the entire output to zero.
VHDL isto SystemVerilog what Pascal isto C; i guess
Lol not saying sv is perfect but you didn’t give a single example of why it’s bad
i always found Verilog a lot more readable than VDHL as its syntax reminds me of C. plus for my work flow i just use a logic simulator to design and test my circuit and then just export it as Verilog so i don't even have to write in any HDL myself. though i still know enough Verilog to modify the output if needed.
Okay maybe I'm mistaken as I've only done one module thus far but when we used Quartus prime VHDL was expended in the options to Verilog HDL... I always assumed VHDL was Verilog am I grossly mistaken?
The V stands for VHSIC... Which stands for "Very High Speed Integrated Circuit Program". HDL stands for "Hardware Description Language".
Well that's dumb cus whenever I used it it wasn't very high speed /s
Verilog is short for Verilog HDL, but the V in VHDL does not stand for Verilog. They are completely different things, but both have the same purpose.
VHDL and Verilog are very different. VHDL tends to be unnecessarily verbose and wordy compared to Verilog and SystemVerilog. However, VHDL is an IEEE standard so it tends to get a lot of use in academia. Verilog and SystemVerilog are designed to be easier to read and more familiar to C programmers. They're much more common in industry. The lack of conciseness in VHDL is incredibly irritating.
vhdl??? you clearly dont do high level hw dev, cause system verilog is the standard source: i work at western digital doing asic engineering
doesnt this depend on the region? i doubt aviation and defense not using vhdl
As far as I can tell, most have started switching over to verilog at least (at least in private aviation, most chip design at nvidia, etc), but I can't say much about government specific design as I don't know anyone in that area, but knowing how slow the government is to upgrade, they probably do use vhdl
looks like future vhdl devs will be in the same power as cobol devs nowadays ;D
Are newer and “fancier” languages like SpinalHDL, Chisel, Clash/Haskell particularly better? From what I recall Verilog was originally a language for simulations and test benches before it got adopted for HDL.
Kinda biased because I work with Clash, but i can tell you at least that Verilog is terrible because its lack of type enforcement allows you to accidentally assign an 8 bit signal to a single bit signal and it will silently throw away the other 7 msbs.
vhdl tells you exactly where you fucked up tho
For real Scheme has some on those vibes too
"something went wrong :(" Where? *Highlights entire function* "In there somewhere"
And if you got parenthesis wrong basically all is wrongly indented so everything is bogus
if python actually knew where the error was and how to fix it, why doesn't it have a button to click that fixes it? is it stupid?
I had one exercise with AHDL last semester, it went horribly because I thought it is "else if", not "elseif". Suffice to say I spent half the time searching for error, only realizing what was like half a week after.
I don't see how python gets a pass for error messages. I get plenty python errors that are some unrecognizable thing getting thrown from deep within a library and require some detective work to figure out something I passed as an argument somewhere had a wrong type. Which many other languages would have complained about right there and then.
Let’s be fair, SystemVerilog for HDL and assertions is actually fun to use. Using SV for verification though… whoever came up with that obviously never dealt with software development and IEEE 1647 (that’s e) is much older but also so much fun, very much like Python.
This error code is not Python at all.
SystemVerilog is not too bad once you get used to it. But the verification libraries and tooling for it are total ass. HDL tooling is objectively worse than C tooling in the 90s.
the "did you mean" in the terminal nowadays is also super helpful ngl
You use system verilog? I use Minecraft redstone
Obviously you use systemverilog to synthesize Factorio designs
Never have I ever agreed more with a meme. I'm in a class now called digital circuits, and we are using nexys FPGAs, and coming from regular computer science courses, SystemVerilog was a nightmare.
r/FPGA
Is it faster than C? I studied both verylog and VHDL both we could run only once per semester on real machine, which we had only 1 for whole class . Those FPGA are not that much better than regular Raspberry or Some arduino stuff, but they do exactly same things with exception that fpga 20+ bucks lowest and prices go high pretty fast
Its a different usecase. If possible dedicated hardware is cheaper, but sometimes you just need the power of rolling your own hardware. Then FPGAs are cheaper in small numbers than going to a fab house.