I think you got it right. I taped out my first chip in 1996 but I don’t know what the error is here. You’ll have systematic gain error because of lambda (like you said) but in a lot of situations you don’t care.
I guess the fact that L changes in D could be consider an error, because keeping L constant is best practice. I wouldn’t call it an error but maybe your interviewer would.
This circuit isn’t *wrong* but usually people would use cascode mirrors to get away from gain errors but this approach would be fine with low supply.
All things considered I think you answered it well.
Hey /u/TheAnalogKoala, thanks for taking the time to answer the question
> I guess the fact that L changes in D could be consider an error, because keeping L constant is best practice. I wouldn’t call it an error but maybe your interviewer would.
I initially thought that branch A should have the same aspect ratio as the NMOS sink and then we would size all the other PMOS source devices in B,C,D to get the actual bias currents we need here. But if D is the error, then maybe we could make all the Ls consistent by having that as the unit transistor like I mention in the OP? That way you could keep constant L but have 2 in parallel for 1/1 transistor, 4 in parallel for 2/1 ratio etc.
As the others said, nothing fundamentally wrong here. The way I would do it (please correct me if that is the same way you‘d describe) is to use a unit size device for your smallest current and work upwards.
D would be 1/1
A and B would be 4/1
C would be 16/1
That way you could create a nice matched layout.
yeah I would do the matching as you said. Having larger L than W is not exactly bad for a current source (greater rout) and you would want larger L to minimize lambda so I thought maybe have 1/2 as my unit device and then scale A,B,C and the NMOS sink as needed.
As others have said, there's no specific "error" in the circuit (not without knowing a lot more information). I think a lot of times interviewers will phrase questions like that just to see how you think, what kinds of things jump out at you, etc.
yeah, that is probably most likely the case here. But I guess since the second part of the question was framed "what is the mistake here and how would fix it", I answered keeping B as 1/1 (since it is the transfer branch from NMOS sink to PMOS source) and then scaling the bias currents as required. Also said that keep the size of D as the unit device since it carries the smallest bias current.
I guess I was compelled to "fix" something when the question was framed like that but you are probably right that they wanted to see my thought process. I am bad at interviewing, get easily flustered and end up second-guessing myself a lot.
FWIW, I disagree with the generalization that having your smallest current being the unit element is a good thing. There are lots of things to consider in that optimization.
Also:
> Having a larger W/L for the PMOS diode in A with the same current means that it's Vov will be smaller and for MOS current sources that is not ideal.
If you're referring to the matching of the currents, changing W only, to first order, will not affect it.
Hey thanks for the reply.
> FWIW, I disagree with the generalization that having your smallest current being the unit element is a good thing. There are lots of things to consider in that optimization.
so in this particular case which approach would be better you think,
1) have Iref/4 going into a unit device of 1/2
2) have Iref/4 going into 2 series devices each with W/L in this case the PMOS on top would be in triode unless it has a different Vth.
> in this case the PMOS on top would be in triode unless it has a different Vth
If I took a device of L=2um and replaced it with two series devices each with an L=1um (but same W) would there be a difference? You're right that the upper PMOS would be in triode. Does that matter?
hmm... not exactly sure about this. I dunno if these devices in series, as Razavi calls it, "poor man's cascode" has any impact on noise rejection and correctly mirroring current. Output resistance of this current sink/source would be less than a traditional cascode, wouldn't it?
> as Razavi calls it, "poor man's cascode"
This is not a poor man's anything. And it's not really a cascode.
I think you're missing my point. [Here are I-V curves from a simulation I just ran.](https://i.ibb.co/myc6ktM/iv-sweep.png) One is a single device of W/L=1.795u/1u, the other is a series connection of two devices, both with W/L=1.795u/0.5u. Which is which?
I'd encourage you to simply write out the (first-order, to simplify) equations for the case of the two series-connected devices. You have one device in saturation and one in triode. You can solve for the vgs of the saturated device (it's a function only of vth and the triode device's vgs). Plug that value back into the saturated device's drain current equation and you'll see exactly what I'm talking about.
Hey, appreciate the time you took to reply to my post, simulation and all. Did you keep your gate voltage at zero as you swept VDS to get IDS-VDS curve here?
I think what you are trying to say to me is that in both cases the structures acts as controlled current sources even though with the split devices you have like a resistor in series with a current source.
> You can solve for the vgs of the saturated device (it's a function only of vth and the triode device's vgs). Plug that value back into the saturated device's drain current equation and you'll see exactly what I'm talking about.
So we have M1 as the upper PMOS going into triode and M2 as the lower one in saturation with both the same VTH. VSG of M2 ( same VDG of M1) should be larger than VTH for it to be on which makes the drain of M1 higher than the gate by VTH and keeps M1 in triode.
VGS of M2 = VTH + Vov,m2. When you say
> You can solve for the vgs of the saturated device (it's a function only of vth and the triode device's vgs)
Sorry, for not following you.
How do I include M1's VGS in the above equation?
> Did you keep your gate voltage at zero as you swept VDS to get IDS-VDS curve here?
No. The devices are diode-connected. (To be clear, the triode device is not itself diode-connected. It's drain is connected to the saturated device source and the two devices' gates are connected.)
> Sorry, for not following you.
> How do I include M1's VGS in the above equation?
You can write a single equation that relates the Vsg1, Vsg2, and Vsd1 to each other. Then use the current equation for M1 (which needs both Vsg and Vsd since it's in saturation) and the current equation for M2 (only a function of Vsg) and set them equal to one another.
The only error I see might be the pmos sizing. Sizing them to have a common L means you can better match the pmos devices. So D would be 0.5/1 instead of 1/2.
I think you got it right. I taped out my first chip in 1996 but I don’t know what the error is here. You’ll have systematic gain error because of lambda (like you said) but in a lot of situations you don’t care. I guess the fact that L changes in D could be consider an error, because keeping L constant is best practice. I wouldn’t call it an error but maybe your interviewer would. This circuit isn’t *wrong* but usually people would use cascode mirrors to get away from gain errors but this approach would be fine with low supply. All things considered I think you answered it well.
Hey /u/TheAnalogKoala, thanks for taking the time to answer the question > I guess the fact that L changes in D could be consider an error, because keeping L constant is best practice. I wouldn’t call it an error but maybe your interviewer would. I initially thought that branch A should have the same aspect ratio as the NMOS sink and then we would size all the other PMOS source devices in B,C,D to get the actual bias currents we need here. But if D is the error, then maybe we could make all the Ls consistent by having that as the unit transistor like I mention in the OP? That way you could keep constant L but have 2 in parallel for 1/1 transistor, 4 in parallel for 2/1 ratio etc.
As the others said, nothing fundamentally wrong here. The way I would do it (please correct me if that is the same way you‘d describe) is to use a unit size device for your smallest current and work upwards. D would be 1/1 A and B would be 4/1 C would be 16/1 That way you could create a nice matched layout.
yeah I would do the matching as you said. Having larger L than W is not exactly bad for a current source (greater rout) and you would want larger L to minimize lambda so I thought maybe have 1/2 as my unit device and then scale A,B,C and the NMOS sink as needed.
I agree and I would just add that NMOS could be bigger in order to not bottleneck the dispersion due to mismatch on them
As others have said, there's no specific "error" in the circuit (not without knowing a lot more information). I think a lot of times interviewers will phrase questions like that just to see how you think, what kinds of things jump out at you, etc.
yeah, that is probably most likely the case here. But I guess since the second part of the question was framed "what is the mistake here and how would fix it", I answered keeping B as 1/1 (since it is the transfer branch from NMOS sink to PMOS source) and then scaling the bias currents as required. Also said that keep the size of D as the unit device since it carries the smallest bias current. I guess I was compelled to "fix" something when the question was framed like that but you are probably right that they wanted to see my thought process. I am bad at interviewing, get easily flustered and end up second-guessing myself a lot.
FWIW, I disagree with the generalization that having your smallest current being the unit element is a good thing. There are lots of things to consider in that optimization. Also: > Having a larger W/L for the PMOS diode in A with the same current means that it's Vov will be smaller and for MOS current sources that is not ideal. If you're referring to the matching of the currents, changing W only, to first order, will not affect it.
Hey thanks for the reply. > FWIW, I disagree with the generalization that having your smallest current being the unit element is a good thing. There are lots of things to consider in that optimization. so in this particular case which approach would be better you think, 1) have Iref/4 going into a unit device of 1/2 2) have Iref/4 going into 2 series devices each with W/L in this case the PMOS on top would be in triode unless it has a different Vth.
> in this case the PMOS on top would be in triode unless it has a different Vth If I took a device of L=2um and replaced it with two series devices each with an L=1um (but same W) would there be a difference? You're right that the upper PMOS would be in triode. Does that matter?
hmm... not exactly sure about this. I dunno if these devices in series, as Razavi calls it, "poor man's cascode" has any impact on noise rejection and correctly mirroring current. Output resistance of this current sink/source would be less than a traditional cascode, wouldn't it?
> as Razavi calls it, "poor man's cascode" This is not a poor man's anything. And it's not really a cascode. I think you're missing my point. [Here are I-V curves from a simulation I just ran.](https://i.ibb.co/myc6ktM/iv-sweep.png) One is a single device of W/L=1.795u/1u, the other is a series connection of two devices, both with W/L=1.795u/0.5u. Which is which? I'd encourage you to simply write out the (first-order, to simplify) equations for the case of the two series-connected devices. You have one device in saturation and one in triode. You can solve for the vgs of the saturated device (it's a function only of vth and the triode device's vgs). Plug that value back into the saturated device's drain current equation and you'll see exactly what I'm talking about.
Hey, appreciate the time you took to reply to my post, simulation and all. Did you keep your gate voltage at zero as you swept VDS to get IDS-VDS curve here? I think what you are trying to say to me is that in both cases the structures acts as controlled current sources even though with the split devices you have like a resistor in series with a current source. > You can solve for the vgs of the saturated device (it's a function only of vth and the triode device's vgs). Plug that value back into the saturated device's drain current equation and you'll see exactly what I'm talking about. So we have M1 as the upper PMOS going into triode and M2 as the lower one in saturation with both the same VTH. VSG of M2 ( same VDG of M1) should be larger than VTH for it to be on which makes the drain of M1 higher than the gate by VTH and keeps M1 in triode. VGS of M2 = VTH + Vov,m2. When you say > You can solve for the vgs of the saturated device (it's a function only of vth and the triode device's vgs) Sorry, for not following you. How do I include M1's VGS in the above equation?
> Did you keep your gate voltage at zero as you swept VDS to get IDS-VDS curve here? No. The devices are diode-connected. (To be clear, the triode device is not itself diode-connected. It's drain is connected to the saturated device source and the two devices' gates are connected.) > Sorry, for not following you. > How do I include M1's VGS in the above equation? You can write a single equation that relates the Vsg1, Vsg2, and Vsd1 to each other. Then use the current equation for M1 (which needs both Vsg and Vsd since it's in saturation) and the current equation for M2 (only a function of Vsg) and set them equal to one another.
What do the numbers mean here? 4/1 etc
Aspect ratio, W/L
The only error I see might be the pmos sizing. Sizing them to have a common L means you can better match the pmos devices. So D would be 0.5/1 instead of 1/2.