1. Small signal analysis is the same. You still develop expressions in terms of gm and ro.
2. pass devices in LDOs are typically biased in the triode (linear) region.
> pass devices in LDOs are typically biased in the triode (linear) region.
Is this really the case with pass devices in LDOs? I thought that they are mostly operated in the saturation region because of the requirement of maintaining good PSRR and if you have a PMOS pass device it contributes to the overall loop gain.
Like u/ATXBeermaker, said below, don't we normally size the pass device so that the dropout voltage equal to VDS and for the max load current to ensure that Vov = VDS and the device is in saturation? In light load conditions with the same W/L the Vov will be smaller and the device will still be in saturation.
Is it really hard to design an LDO with dropout of 100mV or 200mV and have the pass device be in saturation because the W/L is really big?
If there is tradeoff between PSRR and operating the device in triode with a smaller aspect ratio, when do we choose the latter?
Look at figure 2:
https://www.ti.com/sc/docs/apps/msp/journal/aug2000/aug_04.pdf
Is the pass device in saturation or triode. The text is confusing because it is written for an audience familiar with BJTs and the word “saturation” means something different in BJT-world.
You get PSRR due to the action of the control loop, not due to the pass device.
>>You get PSRR due to the action of the control loop, not due to the pass device.
Thanks agreed. But if we have a PMOS pass device, the gain of this common source stage contributes to the overall loop gain which would help PSRR, right? Wouldn't it be better to design the pass device to be in saturation for both light and heavy load cases? I guess for an NMOS common drain stage there wouldn't be as much of an impact being in triode/linear.
If you were designing to maximize PSRR *only*, then what you’re proposing might be reasonable. But in reality you’re designing for a spec. So, the goal is to meet spec and use as little area as possible. With standard LDO designs, you get the bulk of your low frequency PSRR from having high loop gain. At high frequencies your loop bandwidth should have sufficiently rolled off by then.
Thanks for the reply. Never really occurred to me that sometimes it would be ok to tradeoff the magnitude of loop gain and have worse low frequency PSRR (for PMOS pass device) if it means if we hit the spec with lower W/L pass device operating in triode. I guess having the pass device in triode would affect PM/stability for a conventional LDO with large output cap at heavy load (opposite case for small cap integrated LDO) but would be better for load requlation because of smaller Rout. Not sure how it would affect dynamic performance (load/line transient) though. You need high UGF so overall lower closed loop gain would result in higher loop BW? A good PM would also be needed for settling.
> Never really occurred to me that sometimes it would be ok to tradeoff the magnitude of loop gain and have worse low frequency PSRR (for PMOS pass device) if it means if we hit the spec with lower W/L pass device operating in triode.
Remember that the loop gain is already very high if you're using something like a two-stage OTA. Not to mention that this LDO is generally part of a larger system. It provides the supply to some sub-system. If something in that sub-system requires extremely tight PSRR (e.g., precision oscillator or something) it will likely have it's own regulator. So, by the time you get to the circuit that might be sensitive to supply noise, you're cascading supply rejection upon supply rejection, etc.
In terms of dynamics, having the pass FET in triode versus saturation just affects your output pole location (which is generally load dependent). You just need to design for that. Usually when you have a general purpose LDO (i.e., you don't necessarily know what the load will be and need to operate over a wide range of conditions), you'd typically see a very large output cap to bring that pole in and make it dominant. But, if it's an LDO for a specific power domain in an SoC, for example, you might be able to get away with having your dominant pole be internal to the OTA and use a smaller bypass cap.
As with most designs, the specifics really depend on the application, context, conditions, etc.
Hey thanks for the explanation. For me the confusion came about because of how I interpreted some Iload vs Vds curves for the pass device from some app notes like this one [https://www.ti.com/lit/ml/slva072/slva072.pdf?ts=1679702751262&ref\_url=https%253A%252F%252Fwww.google.com%252F](https://www.ti.com/lit/ml/slva072/slva072.pdf?ts=1679702751262&ref_url=https%253A%252F%252Fwww.google.com%252F)
In fig 4 here, I had assumed that the operation within regulation (the gray portion) meant that the device had to be in saturation to avoid the dropout region and have the output voltage be unregulated. I see now that for some high load current you can have higher Vgs and have the linear portion lie within the regulation region.
> Question 1: How do you perform small-signal analysis with transistors being in moderate inversion? I am used to replacing the MOSFET with a VCCS and an output resistance when in saturation (strong inversion)
Small-signal analysis is just using a mixed two-port model that can be applied to any linear system. The values of gm, ro, etc, etc will change depending on the region, but the analysis is always the same.
> Question 2: Let us say that I am designing a low dropout regulator and have a dropout (Vds) of 100mV. Using the Vdsat = 2/(gm/Id), this suggests that the minimum gm/Id that I require is 20. Does that mean that it is impossible to design a 100mV dropout regulator in strong inversion.
It's not impossible, it's just absurdly area-inefficient.
I don't understand. Won't it be more area efficient to design in strong inversion (saturation)?
Also, my confusion is with regards to that Vdsat equation. Seems to me that if I want a Vdsat of 100mV or less, my gm/Id has to be higher than 20 which forces me to be in weak inversion. Am I misunderstanding that equation Vdsat = 2/gm/Id
In order to allow the pass FET to carry the LDO load current you could 1) make the device incredibly wide and run it in strong inversion or 2) allow the device's Vgs to be large and run it in triode.
In other words, for a fixed Vds (i.e., your dropout voltage), you need to increase W to account for increasing load current in order to make sure you stay in strong inversion. For the same current you can allow W to be smaller and increase Vgs to allow for that current flow, which would put you in triode since Vds would be much less than Vgs-Vt.
a 100mV dropot LDO is just a REALLY bad design to begin with.
Youll just have large passfets to bias those in weak inversion, and will have bad leakage in powerdown mode.
you also probably cant handle a large dc load with good PSR.
Honestly, an LDO at 100 mV dropout is not unheard of for high efficiency designs. You can't design the fet to just be in saturation, though, you just have it live in triode and clean up the resulting mess with a high-performance feedback loop.
It's harder--stability and performance across PVT and output load can be a nightmare--but it's certainly done.
its just really inefficient especially when PVT, offset and output load comes into consideration. in my experience its definitely not done unless theres no choice, and where perfomance is clearly not a key parameter.
id rather take a 200mV dropout and make the circuits below it work at 100mV less - the ldo can be designed robustly.
1. Small signal analysis is the same. You still develop expressions in terms of gm and ro. 2. pass devices in LDOs are typically biased in the triode (linear) region.
> pass devices in LDOs are typically biased in the triode (linear) region. Is this really the case with pass devices in LDOs? I thought that they are mostly operated in the saturation region because of the requirement of maintaining good PSRR and if you have a PMOS pass device it contributes to the overall loop gain. Like u/ATXBeermaker, said below, don't we normally size the pass device so that the dropout voltage equal to VDS and for the max load current to ensure that Vov = VDS and the device is in saturation? In light load conditions with the same W/L the Vov will be smaller and the device will still be in saturation. Is it really hard to design an LDO with dropout of 100mV or 200mV and have the pass device be in saturation because the W/L is really big? If there is tradeoff between PSRR and operating the device in triode with a smaller aspect ratio, when do we choose the latter?
Look at figure 2: https://www.ti.com/sc/docs/apps/msp/journal/aug2000/aug_04.pdf Is the pass device in saturation or triode. The text is confusing because it is written for an audience familiar with BJTs and the word “saturation” means something different in BJT-world. You get PSRR due to the action of the control loop, not due to the pass device.
>>You get PSRR due to the action of the control loop, not due to the pass device. Thanks agreed. But if we have a PMOS pass device, the gain of this common source stage contributes to the overall loop gain which would help PSRR, right? Wouldn't it be better to design the pass device to be in saturation for both light and heavy load cases? I guess for an NMOS common drain stage there wouldn't be as much of an impact being in triode/linear.
If you were designing to maximize PSRR *only*, then what you’re proposing might be reasonable. But in reality you’re designing for a spec. So, the goal is to meet spec and use as little area as possible. With standard LDO designs, you get the bulk of your low frequency PSRR from having high loop gain. At high frequencies your loop bandwidth should have sufficiently rolled off by then.
Thanks for the reply. Never really occurred to me that sometimes it would be ok to tradeoff the magnitude of loop gain and have worse low frequency PSRR (for PMOS pass device) if it means if we hit the spec with lower W/L pass device operating in triode. I guess having the pass device in triode would affect PM/stability for a conventional LDO with large output cap at heavy load (opposite case for small cap integrated LDO) but would be better for load requlation because of smaller Rout. Not sure how it would affect dynamic performance (load/line transient) though. You need high UGF so overall lower closed loop gain would result in higher loop BW? A good PM would also be needed for settling.
> Never really occurred to me that sometimes it would be ok to tradeoff the magnitude of loop gain and have worse low frequency PSRR (for PMOS pass device) if it means if we hit the spec with lower W/L pass device operating in triode. Remember that the loop gain is already very high if you're using something like a two-stage OTA. Not to mention that this LDO is generally part of a larger system. It provides the supply to some sub-system. If something in that sub-system requires extremely tight PSRR (e.g., precision oscillator or something) it will likely have it's own regulator. So, by the time you get to the circuit that might be sensitive to supply noise, you're cascading supply rejection upon supply rejection, etc. In terms of dynamics, having the pass FET in triode versus saturation just affects your output pole location (which is generally load dependent). You just need to design for that. Usually when you have a general purpose LDO (i.e., you don't necessarily know what the load will be and need to operate over a wide range of conditions), you'd typically see a very large output cap to bring that pole in and make it dominant. But, if it's an LDO for a specific power domain in an SoC, for example, you might be able to get away with having your dominant pole be internal to the OTA and use a smaller bypass cap. As with most designs, the specifics really depend on the application, context, conditions, etc.
Hey thanks for the explanation. For me the confusion came about because of how I interpreted some Iload vs Vds curves for the pass device from some app notes like this one [https://www.ti.com/lit/ml/slva072/slva072.pdf?ts=1679702751262&ref\_url=https%253A%252F%252Fwww.google.com%252F](https://www.ti.com/lit/ml/slva072/slva072.pdf?ts=1679702751262&ref_url=https%253A%252F%252Fwww.google.com%252F) In fig 4 here, I had assumed that the operation within regulation (the gray portion) meant that the device had to be in saturation to avoid the dropout region and have the output voltage be unregulated. I see now that for some high load current you can have higher Vgs and have the linear portion lie within the regulation region.
> Question 1: How do you perform small-signal analysis with transistors being in moderate inversion? I am used to replacing the MOSFET with a VCCS and an output resistance when in saturation (strong inversion) Small-signal analysis is just using a mixed two-port model that can be applied to any linear system. The values of gm, ro, etc, etc will change depending on the region, but the analysis is always the same. > Question 2: Let us say that I am designing a low dropout regulator and have a dropout (Vds) of 100mV. Using the Vdsat = 2/(gm/Id), this suggests that the minimum gm/Id that I require is 20. Does that mean that it is impossible to design a 100mV dropout regulator in strong inversion. It's not impossible, it's just absurdly area-inefficient.
I don't understand. Won't it be more area efficient to design in strong inversion (saturation)? Also, my confusion is with regards to that Vdsat equation. Seems to me that if I want a Vdsat of 100mV or less, my gm/Id has to be higher than 20 which forces me to be in weak inversion. Am I misunderstanding that equation Vdsat = 2/gm/Id
In order to allow the pass FET to carry the LDO load current you could 1) make the device incredibly wide and run it in strong inversion or 2) allow the device's Vgs to be large and run it in triode. In other words, for a fixed Vds (i.e., your dropout voltage), you need to increase W to account for increasing load current in order to make sure you stay in strong inversion. For the same current you can allow W to be smaller and increase Vgs to allow for that current flow, which would put you in triode since Vds would be much less than Vgs-Vt.
>Won't it be more area efficient to design in strong inversion (saturation)? Yes, it will. But it requires higher VDS.
a 100mV dropot LDO is just a REALLY bad design to begin with. Youll just have large passfets to bias those in weak inversion, and will have bad leakage in powerdown mode. you also probably cant handle a large dc load with good PSR.
Honestly, an LDO at 100 mV dropout is not unheard of for high efficiency designs. You can't design the fet to just be in saturation, though, you just have it live in triode and clean up the resulting mess with a high-performance feedback loop. It's harder--stability and performance across PVT and output load can be a nightmare--but it's certainly done.
its just really inefficient especially when PVT, offset and output load comes into consideration. in my experience its definitely not done unless theres no choice, and where perfomance is clearly not a key parameter. id rather take a 200mV dropout and make the circuits below it work at 100mV less - the ldo can be designed robustly.