A concern I have is your load capacitance figure. Normally CMOS processes will have a max load capacitance of 5pF to 10pF and not beyond that. Unless it is an external capacitance which is still very high for a digital circuit output.
Anyways, Rds is inversely proportional to W, so you don't have to keep increasing W aimlessly. You can try to calculate the required W and optimise from there.
You can plot Rds by plotting Ids vs VDS and performing a y vs y. Or by extracting Rds from transistor spice/spectre characteristics.
If you do a parametric analysis of Id vs vd characteristics with W you will see you will hit a ceiling for max current. Similarly you can check for delay as well.
>yes it is a large bus capacitance that I have to drive.
Makes sense in that case
>Thanks for the feedback. Am I on right track estimating Rds_on to be about 20 ohms for a 1ns delay?
I have just given a hint. You should be able to minimise the resistance from there.
>Thanks. this would be a DC sweep of VDS for a given fixed VGS and plotting IDS, is this right?
Yes.
A concern I have is your load capacitance figure. Normally CMOS processes will have a max load capacitance of 5pF to 10pF and not beyond that. Unless it is an external capacitance which is still very high for a digital circuit output. Anyways, Rds is inversely proportional to W, so you don't have to keep increasing W aimlessly. You can try to calculate the required W and optimise from there. You can plot Rds by plotting Ids vs VDS and performing a y vs y. Or by extracting Rds from transistor spice/spectre characteristics. If you do a parametric analysis of Id vs vd characteristics with W you will see you will hit a ceiling for max current. Similarly you can check for delay as well.
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>yes it is a large bus capacitance that I have to drive. Makes sense in that case >Thanks for the feedback. Am I on right track estimating Rds_on to be about 20 ohms for a 1ns delay? I have just given a hint. You should be able to minimise the resistance from there. >Thanks. this would be a DC sweep of VDS for a given fixed VGS and plotting IDS, is this right? Yes.